1. Field of the Invention
The present invention relates to a method and apparatus for driving a display, and particularly to a method and apparatus for driving a display having display cells with storage capacitors coupled to gate lines.
2. Description of the Prior Art
FIG. 1 is a diagram showing a portion of a conventional display driving circuit. A scan driver 11 provides gate signals GS to display cells 12 for pixel scanning. The display cells 12 receive pixel data carried by data signals DATA from a data driver (not shown) during scan periods. As the display cells 12 are scanned row by row, the pixel data of each frame is stored into the display cells.
The (N+1)th display cell 12 comprises a transistor 121, a liquid crystal cell 122 and a storage capacitor 123. The transistor 121 has a gate coupled to receive the (N+1)th gate signal (N+1)th GS, a drain coupled to receive the data signal DATA and a source coupled to one end of the liquid crystal cell 122. The other end of the liquid crystal cell 122 is coupled to a common electrode (not shown) receiving a common signal Vcom. The storage capacitor 123 has two ends respectively coupled to the source of the transistor 121 and to receive the Nth gate signal Nth GS.
FIG. 2 is a diagram showing timing of the signals of the conventional display driving circuit in FIG. 1. The signal Vcom is an AC signal swinging between voltage levels V1 and V0. Each transistor of the display cells 12 is turned on when the scan driver 11 outputs a high-level gate voltage signal VGH as the gate signal GS and turned off when the scan driver 11 outputs a low-level gate voltage signal VGL as the gate signal GS. Since each of the capacitors 123 is coupled to the gate line of a previous row of the display cells 12, it is necessary for the low-level gate voltage signal VGL to swing with the common signal Vcom in order to maintain a proper voltage difference across the liquid crystal cell 122. The low-level gate voltage signal VGL must be an AC signal swinging between voltage levels V3 and V4 wherein (V3–V4)=(V1–V0). As a result, the gate signal GS is a three-state signal swinging among the voltage levels V2, V3 and V4 wherein V2>V3>V4.
However, the power consumption of the driving circuit using an AC signal as the low-level gate voltage signal VGL is much higher than that using a DC signal.